Nano Scale Single and Double Gate SOI MOSFETs Structures and Compression of Electrical Performance Factors

With the scaling of MOSFETs in to sub-100nm regim, Silicon – on – Insulator (SOI), single gate (SG) and double gate (DG) MOSFETs are expected to replace tradional bulk MOSFETS. These novel MOSFETs devices will be strong contenders in RF applications in wireless communication market. This work is concerned about the device scaling and different design structures of nano scale SOI MOSFETs. The compression of SG and DG configuration and electrical performance demonstrates the superiority of DGMOSFETs: Ideal sub threshold swing, input output Tran conductance and remarkably improved Tran conductance (higher than twice the value in SG – MOSFETs). The experimental data and the difference between SG and DG modes is explained, also the optimization of body thickness and doping profile are elaborated. The impact of energy quantization on gate tunneling current is studied for double and ultra thin body MOSFETs. Reduced vertical electrical field and quantum confinement in the channel of these thin – body devices causes a decrease in gate leakage. But all these are acceptable for channel length above 15 nm. General Terms: Documentation, Performance, Theory.